`timescale 1ns/1ps

module ADC128S102_Driver_tb();

	reg clk;
	reg rst_n;
	reg conv_go;
	reg [2:0] addr;
	wire conv_done;
	wire [11:0] data;
	wire ADC_SCLK;
	wire ADC_CS_N;
	wire ADC_DIN;
	reg ADC_DOUT;

ADC128S102_Driver ADC128S102_Driver(
	.clk(clk),
	.rst_n(rst_n),
	.conv_go(conv_go),
	.addr(addr),
	.conv_done(conv_done),
	.data(data),
	.ADC_SCLK(ADC_SCLK),
	.ADC_CS_N(ADC_CS_N),
	.ADC_DIN(ADC_DIN),
	.ADC_DOUT(ADC_DOUT)
);

	initial clk = 1;
	always #10 clk = ~clk;
	
	initial begin
		rst_n = 0;
		conv_go = 0;
		addr = 0;
		#201;
		rst_n = 1;
		#200;
		conv_go = 1;
		addr = 3;
		#20;
		conv_go = 0;
		// 0 1 2 3
		wait(!ADC_CS_N)// 阻塞
		@(negedge ADC_SCLK);// 等待
		ADC_DOUT = 0;// DB15
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB14
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB13
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB12
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB11
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB10
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB9
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB8
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB7
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB6
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB5
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB4
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB3
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB2
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB1
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB0
		wait(ADC_CS_N);
		#20_000;
		
		conv_go = 1;
		addr = 7;
		#20;
		conv_go = 0;
		// a b c d (12位 高4位无效)
		wait(!ADC_CS_N)
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB15
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB14
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB13
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB12
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB11
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB10
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB9
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB8
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB7
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB6
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB5
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB4
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB3
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB2
		@(negedge ADC_SCLK);
		ADC_DOUT = 0;// DB1
		@(negedge ADC_SCLK);
		ADC_DOUT = 1;// DB0
		wait(ADC_CS_N);
		#2000;
		$stop;
	end
	
endmodule
